TPS54356PWPR datasheet(21/37 Pages) TI2

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TPS54352,TPS54353

TPS54354,TPS54355

TPS54356,TPS54357

SLVS519A − MAY 2004 − REVISED OCTOBER 2004

www.ti.com

Figure 5. The measured closed loop crossover frequency

of 19.95 kHz differs from the calculated value because the

actual output filter capacitor component parameters

differed slightly from the specified data sheet values.

CAPACITOR ESR AND OUTPUT RIPPLE

The amount of output ripple voltage as specified in the

initial design parameters is determined by the

maximum ESR of the output capacitor and the input

ripple current. The output ripple voltage is the inductor

ripple current times the ESR of the output filter so the

maximum specified ESR as listed in the capacitor data

sheet is given by equation 21:

ESR

(MAX) +

IN(MAX)

OUT

0.8

OUT

IN(MAX) *

OUT

*p(MAX)

and the maximum ESR required is 33 m

Ω. In this design,

the aluminum electrolytic capacitor has an ESR of 0.340

Ω, but it is in parallel with an ultra low ESR ceramic

capacitor of 2 m

Ω maximum. The measured output ripple

voltage for this design is approximately 4 mVp−p as shown

in Figure 10.

BIAS AND BOOTSTRAP CAPACITORS

Every TPS54356 design requires a bootstrap capacitor,

C3 and a bias capacitor, C4. The bootstrap capacitor must

be 0.1

µF. The bootstrap capacitor is located between the

PH pins and BOOT pin. The bias capacitor is connected

between the VBIAS pin and AGND. The value should be

1.0

µF. Both capacitors should be high quality ceramic

types with X7R or X5R grade dielectric for temperature

stability. They should be placed as close to the device

connection pins as possible.

LOW-SIDE FET

The TPS54356 is designed to operate using an external

low-side FET, and the LSG pin provides the gate drive

output. Connect the drain to the PH pin, the source to

PGND, and the gate to LSG. The TPS54356 gate drive

circuitry is designed to accommodate most common

n-channel FETs that are suitable for this application. The

SWIFT Designer Software can be used to calculate all the

design parameters for low-side FET selection. There are

some simplified guidelines that can be applied that

produce an acceptable solution in most designs.

The selected FET must meet the absolute maximum

ratings for the application:

D Drain-source voltage (VDSS) must be higher

than the maximum voltage at the PH pin,

which is VINMAX + 0.5 V.

D Gate-source voltage (VGSS) must be greater

than 8 V.

D Drain current (ld) must be greater than 1.1 x

IOUTMAX.

D Drain-source on resistance (RDSON) should be

as small as possible, less than 30 m

W is

desirable. Lower values for RDSON result in

designs with higher efficiencies. It is

important to note that the low-side FET on

time is typically longer than the high-side

FET on time, so attention paid to low-side

FET parameters can make a marked

improvement in overall efficiency.

D Total gate charge (Qg) must be less than 50

nC. Again, lower Qg characteristics result in

higher efficiencies.

D Additionally, check that the device chosen is

capable of dissipating the power losses.

For this design, a Fairchild FDR6674A 30-V n-channel

MOSFET is used as the low-side FET. This particular FET

is specifically designed to be used as a low-side

synchronous rectifier.

POWER GOOD

The TPS54356 is provided with a power good output pin

PWRGD. This output is an open drain output and is

intended to be pulled up to a 3.3-V or 5-V logic supply. A

10-k

Ω, pull-up resistor works well in this application. The

absolute maximum voltage is 6 V, so care must be taken

not to connect this pull-up resistor to VIN if the maximum

input voltage exceeds 6 V.

SNUBBER CIRCUIT

R10 and C11 of the application schematic in Figure 25

comprise a snubber circuit. The snubber is included to

reduce over-shoot and ringing on the phase node when the

internal high-side FET turns on. Since the frequency and

amplitude of the ringing depends to a large degree on

parasitic effects, it is best to choose these component

values based on actual measurements of any design

layout. See literature number SLVP100 for more detailed

information on snubber design.

(21)

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