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SERIAL WRITE OPERATION

SCLK

1

24

SYNC

D

IN

DB23

DB0

DB23

t

4

t

3

t

2

t

1

t

7

t

9

t

6

t

5

t

8

TIMING REQUIREMENTS

(1) (2)

DAC8554

SLAS431B – JUNE 2005 – REVISED OCTOBER 2006

AV

DD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IOVDD = AVDD = 2.7V to 3.6V

40

t1(3)

SCLK cycle time

ns

IOVDD = AVDD = 3.6V to 5.5V

20

IOVDD = AVDD = 2.7V to 3.6V

20

t2

SCLK HIGH time

ns

IOVDD = AVDD = 3.6V to 5.5V

10

IOVDD = AVDD = 2.7V to 3.6V

20

t3

SCLK LOW time

ns

IOVDD = AVDD = 3.6V to 5.5V

10

IOVDD = AVDD = 2.7V to 3.6V

0

t4

SYNC falling edge to SCLK rising edge setup time

ns

IOVDD = AVDD = 3.6V to 5.5V

0

IOVDD = AVDD = 2.7V to 3.6V

5

t5

Data setup time

ns

IOVDD = AVDD = 3.6V to 5.5V

5

IOVDD = AVDD = 2.7V to 3.6V

4.5

t6

Data hold time

ns

IOVDD = AVDD = 3.6V to 5.5V

4.5

IOVDD = AVDD = 2.7V to 3.6V

0

t7

24th SCLK falling edge to SYNC rising edge

ns

IOVDD = AVDD = 3.6V to 5.5V

0

IOVDD = AVDD = 2.7V to 3.6V

40

t8

Minimum SYNC HIGH time

ns

IOVDD = AVDD = 3.6V to 5.5V

20

t9

24th SCLK falling edge to SYNC falling edge

IOVDD = AVDD = 2.7V to 5.5V

130

ns

(1)

All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See Serial Write Operation timing diagram.

(3)

Maximum SCLK frequency is 50MHz at IOVDD = AVDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.

5

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