DAC8554IPW.A datasheet(22/34 Pages) TI2

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DAC8554 to 68HC11 Interface

MICROPROCESSOR INTERFACING

DAC8554 to 8051 Interface

68HC11

(1)

PC7

SCK

MOSI

SYNC

SCLK

(1)Additionalpinsomittedforclarity.

DAC8554

80C51/80L51

(1)

P3.3

TXD

RXD

SYNC

SCLK

(1)Additionalpinsomittedforclarity.

DAC8554

DAC8554 to TMS320 DSP Interface

DAC8554 to Microwire Interface

Microwire

SYNC

SCLK

(1)Additionalpinsomittedforclarity.

DAC8554

MicrowireisaregisteredtrademarkofNationalSemiconductor.

DAC8554

TMS320DSP

SYNC

SCLK

0.1 F

10 F

0.1 F

1mFto10mF

PositiveSupply

FSX

CLKX

OutputA

OutputD

OUT

REF

GND

Reference

Input

DAC8554

SLAS431B – JUNE 2005 – REVISED OCTOBER 2006

Figure 52 shows a serial interface between the

DAC8554 and the 68HC11 microcontroller. SCK of

the 68HC11 drives the SCLK of the DAC8554, while

See Figure 50 for a serial interface between the

the MOSI output drives the serial data line of the

DAC8554 and a typical 8051-type microcontroller.

DAC. The SYNC signal is derived from a port line

The setup for the interface is as follows: TXD of the

(PC7), similar to the 8051 diagram.

8051 drives SCLK of the DAC8554, while RXD

drives the serial data line of the device. The SYNC

signal is derived from a bit-programmable pin on the

port of the 8051. In this case, port line P3.3 is used.

When data are to be transmitted to the DAC8554,

P3.3 is taken LOW. The 8051 transmits data in 8-bit

bytes; thus, only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is

left LOW after the first eight bits are transmitted, then

a second and third write cycle are initiated to

Figure 52. DAC8554 to 68HC11 Interface

transmit the remaining data. P3.3 is taken HIGH

following the completion of the third write cycle. The

8051 outputs the serial data in a format that presents

The 68HC11 should be configured so that its CPOL

the LSB first, while the DAC8554 requires its data

bit is '0' and its CPHA bit is '1'. This configuration

with the MSB as the first bit received. The 8051

causes data appearing on the MOSI output to be

transmit routine must therefore take this into account,

valid on the falling edge of SCLK. When data are

and mirror the data as needed.

being transmitted to the DAC, the SYNC line is held

LOW (PC7). Serial data from the 68HC11 are

transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. (Data are

transmitted MSB first.) In order to load data to the

DAC8554, PC7 is left LOW after the first eight bits

are transferred, then a second and third serial write

operation are performed to the DAC. PC7 is taken

HIGH at the end of this procedure.

Figure 50. DAC8554 to 80C51/80L51 Interface

Figure 53 shows the connections between the

DAC8554 and a TMS320 digital signal processor

(DSP). A single DSP can control up to four

Figure 51 shows an interface between the DAC8554

DAC8554s without any interface logic.

and any Microwire-compatible device. Serial data are

shifted out on the falling edge of the serial clock and

clocked into the DAC8554 on the rising edge of the

SK signal.

Figure 51. DAC8554 to Microwire Interface

Figure 53. DAC8554 to TMS320 DSP

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