AM486DE2 datasheet(28/52 Pages) AMD

28 / 52 page

Am486DE2 Microprocessor

The following is a summary of the key features in the

SMM environment:

s Real mode style address calculation

s 4-Gbyte limit checking

s IF flag is cleared

s NMI is disabled

s TF flag in EFLAGS is cleared; single step traps are

disabled

s DR7 is cleared; debug traps are disabled

s The RSM instruction no longer generates an invalid

op code error

s Default 16-bit op code, register, and stack use

s All bus arbitration (HOLD, AHOLD, BOFF) inputs

and bus sizing (BS8, BS16) inputs operate normally

while the CPU is in SMM.

Executing System Management Mode

Handler

The processor begins execution of the SMI handler at

offset 8000h in the CS segment. The CS Base is initially

30000h, as shown in Table 5.

The CS Base can be changed using the SMM Base

relocation feature

. When the SMI handler is invoked, the

CPU’s PE and PG bits in CR0 are reset to 0. The pro-

cessor is in an environment similar to Real mode, but

without the 64-Kbyte limit checking. However, the de-

fault operand size and the default address size are set

to 16 bits. The EM bit is cleared so that no exceptions

are generated. (If the SMM was entered from Protected

mode, the Real mode interrupt and exception support is

not available.) The SMI handler should not use floating-

point unit instructions until the FPU is properly detected

(within the SMI handler) and the exception support is

initialized.

Because the segment bases (other than CS) are cleared

to 0 and the segment limits are set to 4 Gbyte, the ad-

dress space may be treated as a single, flat 4-Gbyte

linear space that is unsegmented. The CPU is still in

Real mode and when a segment selector is loaded with

a 16-bit value, that value is then shifted left by 4 bits and

loaded into the segment base cache.

In SMM, the CPU can access or jump anywhere within

the 4-Gbyte logical address space. The CPU can also

indirectly access or perform a near jump anywhere with-

in the 4-Gbyte logical address space.

Exceptions and Interrupts with System

Management Mode

When the CPU enters SMM, it disables INTR interrupts,

debug, and single-step traps by clearing the EFLAGS,

DR6, and DR7 registers. This prevents a debug appli-

cation from accidentally breaking into an SMI handler.

Table 4. SMM Initial CPU Core Register Settings

SMM Initial State

General

Purpose

Registers

Unmodified

EFLAGS

0000 0002h

CR0

Bits 0, 2, 3, and 31 cleared (PE, EM, TS,

and PG); remainder unmodified

DR6

Unpredictable state

DR7

0000 0400h

GDTR, LDTR,

IDTR, TSSR

Unmodified

EIP

0000 8000h

Note: Interrupts from INT and NMI are disabled on SMM

entry.

Table 5. Segment Register Initial States

Segment

Selector

Base

Attributes

Limit1

CS2

3000h

30000h

16-bit,

expand up

4 Gbyte

0000h

00000000h

16-bit,

expand up

4 Gbyte

0000h

00000000h

16-bit,

expand up

4 Gbyte

0000h

00000000h

16-bit,

expand up

4 Gbyte

0000h

00000000h

16-bit,

expand up

4 Gbyte

0000h

00000000h

16-bit,

expand up

4 Gbyte

1. The segment limit check is 4 Gbyte instead of the usual

64K.

2. The Selector value for CS remains at 3000h even if the

SMBASE is changed.

AM486DE2 Datasheet(PDF) 28 Page - Advanced Micro Devices

AM486DE2 Datasheet(HTML) 28 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL