SN74HCS237 3- to 8-Line Decoder/Demultiplexer with Address Latches and Schmitt-

Trigger Inputs

1 Features

• Wide operating voltage range: 2 V to 6 V

• Schmitt-trigger inputs allow for slow or noisy input

signals

• Low power consumption

– Typical ICC of 100 nA

– Typical input leakage current of ±100 nA

• ±7.8-mA output drive at 6 V

• Extended ambient temperature range: –40°C to

+125°C, TA

2 Applications

• Memory device selection with shared data bus

• Reduce required number of outputs for chip select

applications

• Route data

3 Description

The SN74HCS237 is a three to eight decoder with

latched address inputs, one standard output strobe

(G0), and one active low output strobe (G 1). When

the latch enable (LE) input is low, the device acts as

a standard three to eight decoder. When the latch

enable (LE) input is high, the address latch retains its

previous state. When the outputs are gated by either

strobe input, they are all forced into the low state.

When the outputs are not disabled by one or both

of the strobe inputs, only the selected output is high

while all others are low.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE (NOM)

SN74HCS237PW

TSSOP (16)

5.00 mm × 4.40 mm

SN74HCS237D

SOIC (16)

9.90 mm × 3.90 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

Input Voltage

Schmitt-trigger

CMOS Input

Response

Waveforms

Standard

CMOS Input

Response

Waveforms

Input Voltage

Input Voltage

Time

Time

Input Voltage

Waveforms

Low Power

Noise Rejection

Supports Slow Inputs

Time

Time

Time

Time

Benefits of Schmitt-trigger inputs

SN74HCS237

SCLS834A – SEPTEMBER 2020 – REVISED JUNE 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.