C

C

TG

C

C

TG

C

C

C

C

C

CLK

D

Q

C

TG

TG

2

1

4

Copyright © 2017, Texas Instruments Incorporated

11

SN74LVC1G79

www.ti.com

SCES220U – APRIL 1999 – REVISED APRIL 2017

Product Folder Links: SN74LVC1G79

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Copyright © 1999–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The SN74LVC1G79 is a single positive-edge-triggered D-type flip-flop. Data at the input (D) is transferred to the

output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the

clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows

for data at the input to be changed without affecting the level at the output, following the hold-time interval.

8.2 Functional Block Diagram

Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and

damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must

be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given

in the Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating

Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a

device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS

input.