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RIGHT-JUSTIFIED AUDIO TIMING DIAGRAM

VALUE of WORD−1

DAC

Updated

t HWF

t SWF

New Word

Starts

t WFUPDAC

t SCK

BIT−14,...., 1

BIT−15 (MSB)

BIT−0

SCLK

DIN

t wsck

t wsck

t hi

t su

t r

t f

BIT−0

BIT−15 (MSB)

BIT−1

BIT−14, ...., 1

WORD−0

WORD−1

WORD−2

New Word

Starts

t WFUPDAC

Temporary

Register

VALUE of WORD−0

PREVIOUS VALUE

changes immediately to new value

FSYNC

changes immediately to new value

** −− New data is transferred to DAC Latch if filter is off;

transferred to filter if filter is on.

DAC Latch or Digital filter input **

DAC Latch or Digital filter input **

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = –5 V, VREF = 4.096 V, unless otherwise

−20

−15

−10

−5

0

5

10

15

20

0

8192

16384

24576

32768

40960

49152

57344

65536

Input Code

−0.5

−0.25

0

0.25

0.5

0

8192

16384

24576

32768

40960

49152

57344

65536

Input Code

DAC8580

SLAS458B – JUNE 2005 – REVISED AUGUST 2005

The DAC8580 serial interface timing uses a single channel (mono) version of right-justified audio format. The

input data is latched into the device input shift register on the rising edge of SCLK, MSB first. The falling edge of

FSYNC latches the last 16 bits of received data (right-justified) from the shift register into a temporary register,

which connects to either the digital filter or the DAC latch. Data in the temporary register is transferred to the

DAC latch (when digital filter is off), or to the digital filter (when the filter is on) on the second rising SCLK edge

after the falling edge of FSYNC. For operating the digital filter, a continuous SCLK is required.

Figure 1. Timing Diagram

noted)

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs

vs

INPUT CODE

INPUT CODE

Figure 2.

Figure 3.

6

Not Recommended For New Designs