VDD

VIN

GND

CS

SDO

SCLK

10 nF

1 F

m

1 F

m

7 V

_

+

R1

C1

R2

5 V

10 W

VDD

VIN

GND

CS

SDO

SCLK

10 nF

1

F

m

GND

IN

OUT

3 V

1

F

m

5 V

REF3030

VDD

VIN

GND

CS

SDO

SCLK

10 nF

1

F

m

VDD

18

ADS7886

SLAS492B – SEPTEMBER 2005 – REVISED AUGUST 2016

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Product Folder Links: ADS7886

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Copyright © 2005–2016, Texas Instruments Incorporated

10 Power Supply Recommendations

The reference voltage for the ADS7886 A/D converter is derived from the supply voltage internally. The supply to

ADS7886 should be driven with a low impedance source and should be decoupled to the ground. Decouple the

VDD with 1-µF ceramic decoupling capacitors, as shown in Figure 32. Always set the VDD supply to be greater

than or equal to the maximum input signal to avoid saturation of codes.

Figure 32. Supply/Reference Decoupling Capacitors

Figure 33. Using the REF3030 Reference

Figure 34. Buffering With the OPA735

11 Layout

11.1 Layout Guidelines

Figure 35 shows a board layout example for the ADS7886. Some of the key considerations are

1. Use a ground plane underneath the device and partition the PCB into analog and digital sections.

2. Avoid crossing digital lines with the analog signal path.

3. The power sources to the device must be clean and well-bypassed. Use 1-µF ceramic bypass capacitors in

close proximity to the supply pin (VDD).