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CD54HC86 Datasheet(PDF) 10 Page - Texas Instruments |
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CD54HC86 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 27 page ![]() 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information In this application, a 2-input XOR gate is used as a phase difference detector as shown in Figure 9-1. The remaining three gates can be used for other applications in the system, or the inputs can be grounded and the channels left unused. The device is used to identify phase difference between a reference clock and another input clock. Whenever the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state. The output is fed into a low-pass filter to obtain a DC representation of the phase difference. 9.2 Typical Application C R Output Input Clock Reference Clo ck Figure 9-1. Typical application schematic 9.2.1 Design Requirements 9.2.1.1 Power Considerations Ensure the desired supply voltage is within the range specified in the Section 6.3. The supply voltage sets the device's electrical characteristics as described in the Section 6.5. The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the CD74HC86 plus the maximum supply current, ICC, listed in the Section 6.5. The logic device can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the maximum total current through GND or VCC listed in the Section 6.1. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are provided to prevent damage to the device. 9.2.1.2 Input Considerations Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the CD74HC86, as specified in the Section 6.5, and the desired input transition rate. A 10-kΩ resistor value is often used due to these factors. CD74HC86, CD54HC86 SCHS137E – AUGUST 1997 – REVISED JUNE 2021 www.ti.com 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CD74HC86 CD54HC86 |
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