5.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

SPECIFICATION

UNIT

DW

DWW

GENERAL

CLR

External clearance(1)

Shortest pin-to-pin distance through air

>8.15

>14.5

mm

CPG

External creepage(1)

Shortest pin-to-pin distance across the package

surfaceHigh Voltage Feature Description

>8.15

>14.5

mm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

>21

>21

μm

CTI

Comparative tracking index

DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A

>600

>600

V

Material group

I

I

Overvoltage category per IEC

60664-1

Rated mains voltage ≤ 600 VRMS

I–IV

I–IV

Rated mains voltage ≤ 1000 VRMS

I–III

I–IV

DIN EN IEC 60747-17 (VDE 0884-17)(2)

VIORM

Maximum repetitive peak isolation

voltage

2121

2828

VPK

VIOWM

Maximum isolation working

voltage

AC voltage (sine wave); Time dependent dielectric

breakdown (TDDB) Test, see Figure 5-1 and Figure 5-2

1500

2000

VRMS

DC voltage

2121

2828

VDC

VIOTM

Maximum transient isolation

voltage

VTEST = 1.2 × VIOTM

t = 60 s (qualification)

t= 1 s (100% production)

8000

8000

VPK

VIMP

Maximum impulse voltage (3)

Tested in air, 1.2/50-us waveform per IEC 62368-1

9800

9800

VPK

VIOSM

Maximum surge isolation voltage

(4)

VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),

1.2/50-μs waveform per IEC 62368-1

12800

12800

VPK

qpd

Apparent charge (5)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.2 × VIOTM = 2545 VPK (DW) and 3394 VPK

(DWW), tm = 10 s

≤5

≤5

pC

Method a: After environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK

(DWW), tm = 10 s

≤5

≤5

Method b: At routine test (100% production);

Vini = 1.2 x VIOTM, tini = 1 s;

Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or

Vpd(m) = Vini, tm = tini (method b2)

≤5

≤5

CIO

Barrier capacitance, input to

output(6)

VIO = 0.4 × sin (2πft), f = 1 MHz

2

2

pF

RIO

Isolation resistance, input to output

(6)

VIO = 500 V, TA = 25°C

>1012

>1012

Ω

VIO = 500 V, 100°C ≤ TA ≤ 125°C

>1011

>1011

VIO = 500 V at TS = 150°C

>109

>109

Pollution degree

2

2

Climatic category

55/125/21

55/125/21

UL 1577

VISO

Withstand isolation voltage

VTEST = VISO = 5700 VRMS, t = 60 s (qualification),

VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%

production)

5700

5700

VRMS

(1)

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal

in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these

specifications.

ISO7842, ISO7842F

SLLSEJ0H – OCTOBER 2014 – REVISED MARCH 2024

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