LM555

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SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015

Typical Application (continued)

VCC = 5 V

Top Trace: Input 4 V/Div.

TIME = 20

μs/DIV.

Middle Trace: Output 2V/Div.

RA = 9.1 kΩ

Bottom Trace: Capa citor 2V/Div.

C = 0.01

μF

Figure 18. Frequency Divider

8.2.2.2 Additional Information

Lower comparator storage time can be as long as 10

μs when pin 2 is driven fully to ground for triggering. This

limits the monostable pulse width to 10

μs minimum.

Delay time reset to output is 0.47

μs typical. Minimum reset pulse width must be 0.3 μs, typical.

Pin 7 current switches within 30 ns of the output (pin 3) voltage.

8.2.3 Application Curves

The data shown below was collected with the circuit used in the typical applications section. The LM555 was

configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:

•

Top Waveform (Yellow) – Capacitor voltage

•

Middle Waveform (Green) – Trigger

•

Bottom Waveform (Purple) – Output

As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low

as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C

value. For this example, the time delay is 5.17 s.

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