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XC2000 Datasheet(PDF) 87 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 87 Page - Infineon Technologies AG |
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87 / 112 page ![]() XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 83 V1.3, 2015-02 4.7.2 Definition of Internal Timing The internal operation of the XC223[04]L is controlled by the internal system clock f SYS. Because the system clock signal f SYS can be generated from a number of internal and external sources using different mechanisms, the duration of the system clock periods (TCSs) and their variation (as well as the derived external timing) depend on the mechanism used to generate f SYS. This must be considered when calculating the timing for the XC223[04]L. Figure 18 Generation Mechanisms for the System Clock Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the example of prescaler operation uses a divider factor of 2:1. The specification of the external timing (AC Characteristics) depends on the period of the system clock (TCS). M C_XC2X_CLOCKGEN Phase Locked Loop Operation (1:N) f IN Direct Clock Drive (1:1) Prescaler Operation (N:1) f SYS f IN f SYS f IN f SYS TCS TCS TCS |
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