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LM5109A

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SNVS412C – APRIL 2006 – REVISED SEPTEMBER 2016

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Feature Description (continued)

(1)

HO is measured with respect to the HS.

(2)

LO is measured with respect to the VSS.

7.3.3 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,

and high-peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-

side output stage is referenced to VSS and the high-side is referenced to HS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-Up and UVLO for more information on UVLO

operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is

dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.

Table 1. INPUT and OUTPUT Logic Table

HI

LI

HO(1)

LO(2)

L

L

L

L

L

H

L

H

H

L

H

L

H

H

H

H

Floating

Floating

L

L