Control

Logic

EN_B1

Thermal

Shutdown

Oscillator

Reference

Voltage

OTP

UVLO

DEFSEL

PG_B1

VIN_B1

10 µF

FB_B1

1.5 µH

SW_B1

VIN

VOUT2

VOUT1

PG_B2

PG_B3

PG_B4

EN_B2

EN_B3

EN_B4

VIN

VIN

VIN

VOUT3

VOUT4

VIN

LDO

10 µF

Buck1

(Active Pulldown)

Buck2

(Active Pulldown)

VIN_B2

10 µF

FB_B2

1.5 µH

SW_B2

10 µF

Buck3

(Active Pulldown)

VIN_B3

10 µF

FB_B3

1.5 µH

SW_B3

10 µF

Buck4

(Active Pulldown)

VIN_B4

10 µF

FB_B4

1.5 µH

SW_B4

10 µF

AVDD

BYP

1 µF

1 µF

LP8728B-Q1

SNVSA70 – FEBRUARY 2015

www.ti.com

7 Detailed Description

7.1 Overview

The LP8728B-Q1 has four integrated high-efficiency buck converters. Each buck converter has individual enable

input and power good output pins. When the first enable pin is pulled high there is a 420-µs start-up delay when

the device wakes up from the shutdown mode and all internal reference blocks are started up. Once reference

blocks have settled, the corresponding buck converter turns on. Buck cores utilize the soft-start feature to limit

the inrush current during start-up. Once a buck output reaches 96% (typical) of the desired output voltage, the

power-good pin is pulled high (see Figure 9). When at least one buck core is active, the remaining buck

converters will start up without any start-up delay.

If the output voltage drops below 93% (typical) of desired voltage due to, for example, an overload condition, the

corresponding power-good pin is pulled low. The power-good signal is always held low for at least 50 ms. When

the enable pin is pulled low, the corresponding buck converter's power good signals are set low, and the buck

converter is instantly shut down. An output capacitor is then discharged through an internal 70-

Ω (typical)

pulldown resistor. The pulldown resistor is connected between buck feedback pin and ground and is only active

when the enable pin is set low. When all enable signals are pulled low, the LP8728B-Q1 enters a low current

shutdown mode.

7.2 Functional Block Diagram

10

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