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LPV7215MF/NOPB Datasheet(PDF) 16 Page - Texas Instruments |
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LPV7215MF/NOPB Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 36 page ![]() CC 1 2 A 1 2 1 3 2 3 V R R V R R R R R R + D = + + 16 LPV7215 SNOSAI6J – SEPTEMBER 2005 – REVISED AUGUST 2016 www.ti.com Product Folder Links: LPV7215 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated 7.4 Device Functional Modes 7.4.1 Capacitive and Resistive Loads The propagation delay is not affected by capacitive loads at the output of the LPV7215. However, resistive loads slightly affect the propagation delay on the falling edge by a reduction of almost 2 µs depending on the load resistance value. 7.4.2 Noise Most comparators have rather low gain. This allows the output to spend time between high and low when the input signal changes slowly. The result is that the output may oscillate between high and low when the differential input is near zero. The exceptionally high gain of this comparator, 120 dB, eliminates this problem. Less than 1 µV of change on the input drives the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the noise unless some hysteresis is provided by positive feedback (see Hysteresis). 7.4.3 Hysteresis To improve propagation delay when low overdrive is needed, hysteresis can be added. 7.4.4 Inverting Comparator With Hysteresis The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage V+ of the comparator as shown in Figure 31. When VIN at the inverting input is less than VA, the voltage at the noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high as V+). The three network resistors can be represented as R1//R3 in series with R2. The lower input trip voltage VA1 is defined as Equation 1. VA1 = VCCR2 / ((R1//R3) + R2) (1) When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as Equation 2. VA2 = VCC (R2//R3) / ((R1+ (R2//R3) (2) The total hysteresis provided by the network is defined as ΔVA = VA1 – VA2, as shown in Equation 3. (3) |
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