STM32U073RCI6 datasheet(25/146 Pages) STMICROELECTRONICS

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USART modes/ features

USART1

USART2

USART3

USART4

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous SPI mode (master/slave)

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wake-up from

Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver enable

3.28

Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed three LPUARTs. The peripherals support asynchronous serial communication with minimum

power consumption, as well as half-duplex single wire communication and modem operations (CTS/RTS). They

allow multiprocessor communication.

The LPUARTs have a clock domain independent of the CPU clock, and can wake up the system from Stop mode

using baud rates up to 220 Kbaud. The Stop mode wake-up events are programmable and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in

Stop mode, the LPUARTs can wait for an incoming frame while having an extremely low energy consumption. To

reach higher baud rates, a higher speed clock can be used.

The LPUART interface can be served by the DMA controller.

3.29

Serial peripheral interface (SPI)

The devices contain three SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex,

full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is

configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC

calculation.

The SPI peripherals can be served by the DMA controller.

Table 10. SPI implementation

X: supported

SPI modes/ features

SPI1

SPI2

SPI3

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I2S mode

TI mode

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

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