ADS1601IPFBR datasheet(18/31 Pages) TI2

18 / 31 page

10 F

0.1 F

10 F

0.1 F

10 F

0.1 F

VREFP

VMID

VCAP

VREFN

392W

OPA2822

ADS1601

0.001 F

392W

OPA2822

0.001 F

392W

OPA2822

0.001 F

2.5V

AGND

+0.94V

REF

-0.94V

REF

0.94V

(

)

£ -

REF

0.94V

(

)

ADS1601

SBAS322D

– DECEMBER 2004 – REVISED OCTOBER 2011

www.ti.com

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

INPUT SIGNAL

MAXIMUM

MAXIMUM ALLOWABLE

FREQUENCY

AMPLITUDE

CLOCK SOURCE JITTER

500kHz

–0.5dB

6ps

500kHz

–20dB

60ps

100kHz

–0.5dB

30ps

100kHz

–20dB

300ps

DATA FORMAT

The

16-bit

output

data

are

binary

two

’s

complement format as shown in Table 2. When the

input is positive out-of-range, exceeding the positive

full-scale value of +0.94VREF, the output clips to all

7FFFh and the OTR output goes high.

Likewise, when the input is negative out-of-range by

going

below

the

negative

full-scale

value

–0.94VREF, the output clips to 8000h and the OTR

output goes high. The OTR remains high while the

input signal is out-of-range.

Figure 42. Recommended Buffer Circuit When

Using an External Reference

Table 2. Output Code versus Input Signal

INPUT SIGNAL (INP

–

IDEAL OUTPUT

CLOCK INPUT (CLK)

INN)

CODE(1)

OTR

≥ +0.94VREF (> 0dB)

7FFFh

The ADS1601 requires an external clock signal to be

–0.94VREF (0dB)

7FFFh

applied to the CLK input pin. The sampling of the

modulator is controlled by this clock signal. As with

001h

any high-speed data converter, a high quality clock is

essential for optimum performance. Crystal clock

0000h

oscillators are the recommended CLK source; other

sources, such as frequency synthesizers, are usually

FFFFh

inadequate. Make sure to avoid excess ringing on the

CLK input; keeping the trace as short as possible

helps.

8000h

Measuring high-frequency, large amplitude signals

requires tight control of clock jitter. The uncertainty

during sampling of the input from clock jitter limits the

8000h

maximum achievable SNR. This effect becomes more

pronounced

with

higher

frequency

and

larger

(1) Excludes effects of noise, INL, offset and gain errors.

magnitude

inputs.

Fortunately,

the

ADS1601

oversampling topology reduces clock jitter sensitivity

OUT-OF-RANGE INDICATION (OTR)

over that of Nyquist rate converters such as pipeline

If the output code exceeds the positive or negative

and successive approximation converters by a factor

full-scale, the out-of-range digital output OTR will go

√16.

high on the falling edge of SCLK. When the output

In order to not limit the ADS1601 SNR performance,

code returns within the full-scale range, OTR returns

keep the jitter on the clock source below the values

low on the falling edge of SCLK.

shown in Table 1. When measuring lower frequency

and lower amplitude inputs, more CLK jitter can be

tolerated. In determining the allowable clock source

jitter, select the worst-case input (highest frequency,

largest amplitude) that will be seen in the application.

ADS1601IPFBR Datasheet(PDF) 18 Page - Texas Instruments

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