ADS5500IPAPR datasheet(26/37 Pages) TI2

26 / 37 page

www.ti.com

OUTPUT INFORMATION

INTERNAL DLL

ADS5500

SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007

DLL OFF mode described in the Serial Interface

Programming section. The Typical Performance

Curves show the performance obtained in both

modes of operation: DLL ON (default) and DLL OFF.

In either of the two modes, the device enters

power-down mode if no clock or slow clock is

provided. The limit of the clock frequency where the

device functions properly with default settings is

ensured to be over 2 MHz.

The ADC provides 14 data outputs (D13 to D0, with

D13 being the MSB and D0 the LSB), a data-ready

signal (CLKOUT, pin 43), and an out-of-range

indicator (OVR, pin 64) that equals one when the

output reaches the full-scale limits.

Figure 49. AC Performance vs Clock Duty Cycle

Two different output formats (straight offset binary or

Bandpass filtering of the clock source can help

two's complement) and two different output clock

produce a 50% duty cycle clock and reduce the

polarities (latching output data on rising or falling

effect of jitter. When using a sinusoidal clock, the

edge of the output clock) can be selected by setting

clock jitter further improves as the amplitude is

DFS (pin 40) to one of four different voltages.

increased. In that sense, using a differential clock

Table 3 details the four modes. In addition, output

allows for the use of larger amplitudes without

enable control (OE, pin 41, active high) is provided to

exceeding the supply rails and absolute maximum

put the outputs into a high-impedance state.

ratings of the ADC clock input. Figure 50 shows the

In the event of an input voltage overdrive, the digital

performance variation of the device versus input

outputs go to the appropriate full scale level. For a

clock amplitude. For detailed clocking schemes

positive overdrive, the output code is 0x3FFF in

based on transformer or PECL-level clocks, see the

straight offset binary output format, and 0x1FFF in

ADS5500EVM user's guide (SLWU010), available for

2's complement output format. For a negative input

download from www.ti.com.

overdrive, the output code is 0x0000 in straight offset

binary

output

format

and

0x2000

two's

complement output format. These outputs to an

overdrive signal are ensured through design and

characterization.

The output circuitry of the ADS5500, by design,

minimizes the noise produced by the data switching

transients and, in particular, its coupling to the ADC

analog circuitry. Output D4 (pin 51) senses the load

capacitance and adjusts the drive capability of all the

output pins of the ADC to maintain the same output

slew rate described in the timing diagram of Figure 1.

Care should be taken to ensure that all output lines

(including CLKOUT) have nearly the same load as

D4 (pin 51). This circuit also reduces the sensitivity

of the output timing versus supply voltage or

temperature. Placing external resistors in series with

Figure 50. AC Performance vs Clock Amplitudes

the outputs is not recommended.

The timing characteristics of the digital outputs

change for sampling rates below the 125 Msps

maximum sampling frequency. Table 5 through

In order to obtain the fastest sampling

rates

Table

show

the

values

various

timing

achievable with the ADS5500, the device uses an

parameters for lower sampling frequencies, both with

internal digital delay lock loop (DLL). Nevertheless,

DLL on and off.

the limited frequency range of operation of DLL

degrades the performance at clock frequencies

below 60 Msps. In order to operate the device below

60 Msps, the internal DLL must be shut off using the

Submit Documentation Feedback

ADS5500IPAPR Datasheet(PDF) 26 Page - Texas Instruments

ADS5500IPAPR Datasheet(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL