List of figures

TDA7498MV

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DocID016505 Rev 6

List of figures

Figure 1: Internal block diagram .................................................................................................................5

Figure 2: Pin connections (top view, PCB view) .........................................................................................6

Figure 3: Test board..................................................................................................................................11

Figure 4: Output power (THD = 10%) vs. supply voltage .........................................................................12

Figure 5: THD vs. output power ................................................................................................................12

Figure 6: THD vs. frequency (1 W) ...........................................................................................................12

Figure 7: THD vs. frequency (100 mW) ....................................................................................................12

Figure 8: Frequency response ..................................................................................................................13

Figure 9: FFT performance (0 dBFS) .......................................................................................................13

Figure 10: FFT performance (-60 dBFS) ..................................................................................................13

Figure 11: Output power (THD = 10%) vs. supply voltage .......................................................................14

Figure 12: THD vs. output power ..............................................................................................................14

Figure 13: THD vs. frequency (1 W) .........................................................................................................14

Figure 14: THD vs. frequency (100 mW) ..................................................................................................14

Figure 15: Frequency response ................................................................................................................15

Figure 16: FFT performance (0 dB) ..........................................................................................................15

Figure 17: FFT performance (-60 dB).......................................................................................................15

Figure 18: Application circuit.....................................................................................................................16

Figure 19: Standby and mute circuits .......................................................................................................17

Figure 20: Turn on/off sequence for minimizing speaker “pop” ................................................................17

Figure 21: Input circuit and frequency response ......................................................................................18

Figure 22: Master and slave connection...................................................................................................19

Figure 23: Typical LC filter for an 8 Ω speaker.........................................................................................20

Figure 24: Typical LC filter for a 6 Ω speaker ...........................................................................................20

Figure 25: Behavior of pin DIAG for various protection conditions...........................................................21

Figure 26: PowerSSO-36 EPU package outline .......................................................................................23