5

DAC80004, DAC70004, DAC60004

www.ti.com

SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

Product Folder Links: DAC80004 DAC70004 DAC60004

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Copyright © 2016–2017, Texas Instruments Incorporated

(1)

200 mV headroom is required between REFIN and VDD when 2.7 V

≤ VDD ≤ 4.5 V.

(2)

Output unloaded

(3)

End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 -

DAC60004, Output unloaded.

(4)

With 100 mV headroom between DAC output and VDD.

7.5 Electrical Characteristics

All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN

(1) ≤ VDD, R

load = 5 kΩ to

GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE(2)

Resolution

DAC80004

16

Bits

DAC70004

14

DAC60004

12

INL

Relative accuracy(3)

±1

LSB

DNL

Differential nonlinearity(3)

Ensured monotonic

±1

LSB

TUE

Total unadjusted error(3)

TA = +20°C to +40°C

1.5

mV

TA = –40°C to +125°C

2

ZCE

Zero code error

TA = –40°C to +125°C, Code 0d into

DAC

±0.2

±2

mV

TA = +25°C, Code 0d into DAC

±0.1

ZCE-TC

Zero code error TC

TA = –40°C to +125°C

±5

µV/°C

OE

Offset error(3)

TA = +20°C to +40°C

±1.2

mV

TA = –40°C to +125°C

±0.2

±1.8

TA = +25°C

±0.2

OE-TC

Offset error drift

TA = –40°C to +125°C

±4

µV/°C

FSE

Full-scale error(4)

TA = +20°C to +40°C, Code 65535d

into DAC

±0.05

%FSR

TA = –40°C to +125°C, Code

65535d into DAC

±0.01

±0.07

%FSR

TA = +25°C

±0.01

FSE-TC

Full-scale error drift(4)

TA = –40°C to +125°C

±2

ppm

FSR/°C

GE

Gain error(3)

TA = –40°C to +125°C

±0.005

±0.05

%FSR

TA = +25°C

±0.005

GE-TC

Gain drift

TA = –40°C to +125°C

±2

ppm

FSR/°C

Output voltage drift vs.Time

TA = +25°C, Vout = ¾ of full scale,

1900 hr

20

ppm FSR

Load Regulation

TA = +25°C, Vout =Mid Scale

0.003%

PSRR

DC Power supply rejection ratio(4)

TA = +25°C, Vout = full scale

–92

dB