L9954LXP datasheet(8/35 Pages) STMICROELECTRONICS

8 / 35 page

Block diagram and pin description

L9954LXP

8/35

Doc ID 16186 Rev 3

VCC

Logic supply voltage

For this input a ceramic capacitor as close as possible to GND is

recommended.

CLK

Serial clock input

This input controls the internal shift register of the SPI and requires

CMOS logic levels.

Charge pump output

This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection.

PWM1

PWM1 input

This input signal can be used to control the drivers OUT1-OUT4 and

OUT6 by an external PWM signal.

OUT4,

OUT5

High-side driver output 4 and 5

Each output is built by a high-side switch and is intended for resistive

loads, hence the internal reverse diode from GND to the output is

missing. For ESD reason a diode to GND is present but the energy

which can be dissipated is limited. Each high-side driver is a power

DMOS transistor with an internal parasitic reverse diode from each

output to VS (bulk-drain-diode). Each output is over-current and open-

load protected.

15, 16, 17, 20,

21, 22, 23, 24,

29, 30, 34

Not connected pins.

Table 2.

Pin definitions and functions (continued)

Symbol

Function

L9954LXP Datasheet(PDF) 8 Page - STMicroelectronics