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STA335BWQS Datasheet(PDF) 40 Page - STMicroelectronics |
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STA335BWQS Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 72 page ![]() Register description STA335BWQS 40/72 For each configuration the PWM from the digital driver is mapped in a different way to the power stage: 2.0 channels, two full bridges (OCFG = 00) DDX1A : OUT1A DDX1B : OUT1B DDX2A : OUT2A DDX2B : OUT2B DDX3A : OUT3A DDX3B : OUT3B DDX4A : OUT4A DDX4B : OUT4B DDX1A/1B configured as ternary DDX2A/2B configured as ternary DDX3A/3B configured as line-out ternary DDX4A/4B configured as line-out ternary. On channel 3 line out (LOC bits = 00) the same data as channel 1 processing are sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing are sent. In this configuration, no volume control or EQ have effect on channel 3 and 4. Figure 17 shows the PWM slot phases for this configuration. Figure 17. 2.0 channels (OCFG = 00) PWM slots. OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B Obsolete Product(s) - Obsolete Product(s) |
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