L9300 datasheet(176/178 Pages) STMICROELECTRONICS

176 / 178 page

List of figures

Figure 1.

Internal block diagram ............................................................... 3

Figure 2.

Internal block diagram with internal supply domain partitioning ................................... 4

Figure 3.

Pin out (exposed pad down top view, exposed pad up bottom view) ............................... 5

Figure 4.

Internal supply power-up timings....................................................... 11

Figure 5.

Wake up through WAKE pin .......................................................... 12

Figure 6.

Power down from WAKE pin.......................................................... 14

Figure 7.

Power down from power hold condition .................................................. 15

Figure 8.

Power down from not refreshing keep-alive bit ............................................. 16

Figure 9.

Device state block diagram .......................................................... 17

Figure 10.

VDD1 regulator circuit .............................................................. 19

Figure 11.

VDD2 linear or tracking regulator ...................................................... 22

Figure 12.

VDD3 linear regulator with external N-ch FET.............................................. 25

Figure 13.

VDD4 regulator linear configuration ..................................................... 27

Figure 14.

TRK regulators ................................................................... 30

Figure 15.

WSI control blocks ................................................................ 31

Figure 16.

WS compatibility .................................................................. 32

Figure 17.

Standstill operation when PWM two edges per tooth is selected ................................. 33

Figure 18.

Definition of speed pulse and data log bits ................................................ 34

Figure 19.

Signal monitoring: normal speed ....................................................... 34

Figure 20.

Signal monitoring: high Speed ........................................................ 35

Figure 21.

Signal monitoring: standstill .......................................................... 35

Figure 22.

Reset generation ................................................................. 41

Figure 23.

Reset power up/down .............................................................. 42

Figure 24.

VDD3 reset conditioning ............................................................ 42

Figure 25.

VDD4 reset conditioning ............................................................ 42

Figure 26.

Internal supply concept ............................................................. 45

Figure 27.

High–side and low–side configuration ................................................... 49

Figure 28.

Hardware control configuration ........................................................ 50

Figure 29.

Dither functionality ................................................................ 52

Figure 30.

Software mode filter time ............................................................ 54

Figure 31.

Software control loop configuration ..................................................... 54

Figure 32.

Driver timing chart HS_config=0, SW_cntr=1 .............................................. 55

Figure 33.

Driver timing chart HS_config=1, SW_cntr=1 .............................................. 55

Figure 34.

Driver behavior in short to GND condition: HS_config=1, SW_cntr=1, OVC_R=1...................... 57

Figure 35.

Driver behavior in short to battery condition: HS_config=1, SW_cntr=1, OVC_R=1 .................... 58

Figure 36.

LS configuration diagnostic .......................................................... 59

Figure 37.

HS configuration diagnostic .......................................................... 60

Figure 38.

Failsafe concept .................................................................. 65

Figure 39.

Pump PWM programming ........................................................... 66

Figure 40.

Pump motor concept ............................................................... 67

Figure 41.

Charge pump .................................................................... 69

Figure 42.

GPO driver...................................................................... 71

Figure 43.

PRUN WD block diagram............................................................ 75

Figure 44.

PRUN WD initialization ............................................................. 75

Figure 45.

WD time-out timings at power up ...................................................... 76

Figure 46.

WD enable/disable function .......................................................... 77

Figure 47.

WD PRUN over frequency detection .................................................... 78

Figure 48.

Reset latch block diagram ........................................................... 79

Figure 49.

Reset-Latch timing diagram .......................................................... 80

Figure 50.

WD block diagram................................................................. 82

Figure 51.

Monodirectional Timing check evolution .................................................. 83

Figure 52.

Bidirectional Timing check evolution .................................................... 83

Figure 53.

WD FSM evolution. WD_TO_RST_EN =0 ................................................ 85

L9300

List of figures

DS12258 - Rev 5

page 176/178

L9300 Datasheet(PDF) 176 Page - STMicroelectronics

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