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INA260

SBOS656C – JULY 2016 – REVISED DECEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

8.6.5 Mask/Enable Register (06h) (Read/Write)

The Mask/Enable Register selects the function that is enabled to control the ALERT pin as well as how that pin

functions. If multiple functions are enabled, the highest significant bit position Alert Function (D15-D11) takes

priority and responds to the Alert Limit Register.

Figure 34. Mask/Enable Register (06h) (Read/Write)

15

14

13

12

11

10

9

8

OCL

UCL

BOL

BUL

POL

CNVR

—

—

0

0

0

0

0

0

0

0

R/W

R

7

6

5

4

3

2

1

0

—

—

—

AFF

CVRF

OVF

APOL

LEN

0

0

0

0

0

0

0

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Mask/Enable Register Field Descriptions

Bit

Field

Type

Reset

Description

15

OCL

R/W

0

Over Current Limit

Setting this bit high configures the ALERT pin to be asserted if the current

measurement following a conversion exceeds the value programmed in the Alert

Limit Register.

14

UCL

R/W

0

Under Current Limit

Setting this bit high configures the ALERT pin to be asserted if the current

measurement following a conversion drops below the value programmed in the

Alert Limit Register.

13

BOL

R/W

0

Bus Voltage Over-Voltage

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

measurement following a conversion exceeds the value programmed in the Alert

Limit Register.

12

BUL

R/W

0

Bus Voltage Under-Voltage

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

measurement following a conversion drops below the value programmed in the

Alert Limit Register.

11

POL

R/W

0

Power Over-Limit

Setting this bit high configures the ALERT pin to be asserted if the Power

calculation made following a bus voltage measurement exceeds the value

programmed in the Alert Limit Register.

10

CNVR

R/W

0

Conversion Ready

Setting this bit high configures the ALERT pin to be asserted when the Conversion

Ready Flag, Bit 3, is asserted indicating that the device is ready for the next

conversion.

9–5

—

R

00000

Not used.

4

AFF

R

0

Alert Function Flag

While only one Alert Function can be monitored at the ALERT pin at a time, the

Conversion Ready can also be enabled to assert the ALERT pin. Reading the Alert

Function Flag following an alert allows the user to determine if the Alert Function

was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit

clears only when the Mask/Enable Register is read. When the Alert Latch Enable

bit is set to Transparent mode, the Alert Function Flag bit is cleared following the

next conversion that does not result in an Alert condition.

3

CVRF

R

0

Conversion Ready

Although the device can be read at any time, and the data from the last conversion

is available, the Conversion Ready Flag bit is provided to help coordinate one-shot

or triggered conversions. The Conversion Ready Flag bit is set after all

conversions, averaging, and multiplications are complete. Conversion Ready Flag

bit clears under the following conditions:

1.) Writing to the Configuration Register (except for Power-Down selection)

2.) Reading the Mask/Enable Register