VNH9045AQ datasheet(39/40 Pages) STMICROELECTRONICS

39 / 40 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Configuration diagram (bottom view) ..................................................... 4

Figure 3.

Current convention ................................................................. 5

Figure 4.

Current sense timings (current sense mode)............................................... 11

Figure 5.

tDSTKON ........................................................................ 11

Figure 6.

Definition of the low-side switching times ................................................. 12

Figure 7.

Definition of the high-side switching times ................................................ 12

Figure 8.

Low-side turn-on delay time .......................................................... 13

Figure 9.

Time to shutdown for the low-side driver ................................................. 13

Figure 10.

Input reset time for HSD-fault unlatch ................................................... 14

Figure 11.

Input reset time for LSD-fault unlatch.................................................... 14

Figure 12.

PH_OUT delay time on out switch ...................................................... 15

Figure 13.

PH_OUT delay time on SELx change ................................................... 15

Figure 14.

OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) ............................... 16

Figure 15.

State diagram.................................................................... 18

Figure 16.

Typical application schematic ......................................................... 20

Figure 17.

Current sense block diagram ......................................................... 21

Figure 18.

VSENSE vs ILOAD at VCC = 13 V........................................................ 22

Figure 19.

QFN 6x6 26+2L PCB 6 layers......................................................... 27

Figure 20.

Chipset configuration............................................................... 28

Figure 21.

HSD thermal impedance junction ambient single pulse ....................................... 29

Figure 22.

LSD thermal impedance junction ambient single pulse........................................ 30

Figure 23.

Thermal fitting model ............................................................... 30

Figure 24.

QFN 6x6 triple pad 26+2L package outline ................................................ 32

Figure 25.

QFN 6x6 triple pad 26+2L package sections............................................... 33

VNH9045AQ

List of figures

DS14535 - Rev 6

page 39/40

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