VDD

V(BOT)

REG

Time

Case 1

Case 2

Return to

default

state

Unknown

state

0 V

Return to

default

state

Unknown

state

Case 3

Case 4

Slew rate < 3.6 kV/s

Slew rate > 3.6 kV/s

Slew rate < 3.6 kV/s

Slew rate > 3.6 kV/s

1.75 V

VDD

Figure 7-2. Brownout Behavior

7.4 Device Functional Modes

7.4.1 FIFO Mode

The DRV2665 device includes a 100-byte FIFO for real-time haptic waveform playback. The FIFO mode accepts

8-bit digital haptic waveform data over an I2C compatible bus and writes it into an on-chip FIFO. The data is read

out of the FIFO automatically at an 8-kHz sampling rate and fed into a digital-to-analog converter (DAC). The

DAC then drives the high-voltage amplifier. This mode is utilized when the user writes directly to the I2C FIFO

entry address (0x0B). When the first data byte is written to the FIFO, the device goes through the proper start-up

sequence and begins outputting the waveform automatically. An internal timing sequence waits approximately

2 ms before the first data is sent through the DAC and output by the device. It is important that the data

values start and end at or near the mid-scale code (0x00) to avoid large steps at the beginning and end of the

waveform. When the FIFO is empty, the device waits for the timeout period , and then enters into an idle state.

Because the speed of the serial interface could be faster than the read-out rate of the FIFO, the device does

not acknowledge, or NAK, if the FIFO is full during a FIFO write transaction. If at any time the FIFO becomes

completely full, the FIFO_FULL bit is set. When in this condition, the FIFO cannot accept more data without

overwriting previous data that has not yet been played. If this occurs, the user must wait until data has had a

chance to empty from the FIFO before sending more data. The data must be re-sent starting at the byte that

received a NAK.

Any multi-byte I2C write to the FIFO register is treated as a continuous write to the FIFO. Multi-byte writes are

preferred for optimum performance. The FIFO interprets the incoming data as twos complement. This means the

maximum full-scale code is 0x7F, the maximum negative voltage is 0x80, and the mid-scale is 0x00.

7.4.2 Analog Playback Mode

In analog playback mode the signal in the IN+/IN– inputs is amplified and played through the high-voltage

amplifier. When the INPUT_MUX bit is set, the DRV2665 device switches the analog inputs (IN+/IN–) to the

high-voltage amplifier. While in the analog mode, the gain is still register-selectable. Also, the high-voltage

amplifier enable is controlled directly through the EN_OVERRIDE bit, so the EN_OVERRIDE bit must be set for

the boost and amplifier to be active.

7.4.3 Low Voltage Operation Mode

The lowest gain setting is optimized for 50 VPP with a boost voltage of 30 V. Some applications may not need

50 VPP, so the user may elect to program the boost converter as low as 15 V to improve efficiency. When using

boost voltages lower than 30 V, consider the following: First, to reduce boost ripple to an acceptable level, a

50-V rater, 0.22-µF boost capacitor is recommended. Second, the maximum code range of the digital interface

is limited. For example, the user may elect to program the boost voltage to 25 V, and plan for a maximum drive

signal of 40 VPP at the actuator. Any digital code given to the FIFO that is greater than 20 VP / 25 VP x 127

= ±102 may induce clipping, so the user must only send digital codes between –102 and 102. Use of codes

outside this range, for this example, may clip or drive the actuator beyond its rating.

www.ti.com

DRV2665

SLOS740C – MAY 2012 – REVISED JANUARY 2023

Copyright © 2023 Texas Instruments Incorporated

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