7.3 Power Supply Recommendations

The nominal performance of the INA122 is specified with a single supply voltage (+VS) of 5V and reference

voltage (REF) connected to ground. The device operates using power supplies from 2.2V to 36V in single or dual

supply.

CAUTION

Supply voltages higher than 36V (±18V) can permanently damage the device. Parameters that vary

over supply voltage or temperature are shown in Typical Characteristics of this data sheet.

7.4 Layout

7.4.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals. Even a slight mismatch in parasitic capacitance at the gain

setting pins can degrade CMRR over frequency. For example, in applications that implement gain switching

using switches or PhotoMOS® relays to change the value of RG, select the component so that the switch

capacitance is as small as possible. Take care to minimize the capacitance mismatch between the RG pins as

much as possible.

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and through the

device. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed

to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 7-6, keeping RG close

to the device minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• Cleaning the PCB following board assembly is recommended for best performance.

• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low-temperature,

post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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INA122

SBOS069A – OCTOBER 1997 – REVISED DECEMBER 2024

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