TDA7478

Output timing

Doc 10679 Rev 4

7/11

3

Output timing

The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data.

According to the internal PLL lock condition data change can result on the falling or on the

rising clock edge. (see Figure 3). Whichever clock edge is used by the decoder (rising or

falling edge) the data will remain valid for 416.7

μs after the clock transition.

Figure 3.

RDS timing diagram