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SPC570S40E1 Datasheet(PDF) 7 Page - STMicroelectronics |
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SPC570S40E1 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 75 page ![]() DocID024492 Rev 7 7/75 SPC570S40Ex, SPC570S50Ex Introduction 74 Data flash memory (suitable for EEPROM emulation) 32 KB UTEST flash memory 8 KB Boot assist flash (BAF) 8 KB CRC 1 LINFlexD Up to 2 FlexCAN Up to 2 DSPI 3 eTimer 4 x 6 channels ADC (SAR) 2(3) CTU (Cross Triggering Unit) 1 Temperature sensor 1 Self-test control unit (memory and logic BIST) 1 FCCU 1 MEMU 1 PLL Dual PLL with FM Nexus 3(4) Sequence processing unit (SPU) 1 External power supplies 5V(5) 3.3 V(5) Junction temperature −40 to 150 °C 165 °C grade optional (6) Packages Device SPC570SxxE3 eTQFP100 Device SPC570SxxE1 eTQFP64 1. Includes user programmable CPU core and one safety core. The two e200z0h processors in the lockstep pair run at 80 MHz. The e200z0h is compatible with the Power Architecture embedded specification. 2. SMPU with process ID support extension 3. One ADC can be used as supervisor ADC 4. Including trace for the crossbar masters (data & instruction trace on core and data trace on eDMA). 4 MDO pin Nexus trace port. 5. All I/Os can be supplied at 3.3 V or 5 V (mutually exclusive) 6. Refer to technical note "SPC570S family - High Temperature "D" Grade (DocID031416 - TN1262)" for associated specification limitation. Table 1. SPC570Sx device feature summary (Family Superset Configuration) (continued) Feature Description |
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