LP5569 datasheet(8/93 Pages) TI2

8 / 93 page

LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

www.ti.com

Product Folder Links: LP5569

Submit Documentation Feedback

7.10 Serial-Bus Timing Requirements (SDA, SCL), See Figure 1

2C fast mode

MIN

MAX

UNIT

ƒSCL

Clock frequency

400

kHz

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup time for a repeated START condition

600

Data hold time

Data setup time

100

Rise time of SDA and SCL

20 + 0.1Cb

300

Fall time of SDA and SCL

15 + 0.1Cb

300

Setup time for STOP condition

600

Bus-free time between a STOP and a START condition

1.3

µs

Capacitive load for each bus line

200

7.11 External Clock Timing Requirements (CLK), See Figure 2

over operating ambient temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

ƒCLK

Clock frequency

32.7

kHz

tCLKH

High time

µs

tCLKL

Low time

µs

Clock rise time, 10% rising edge to 90% rising edge

µs

Clock fall time, 90% falling edge to 10% falling edge

µs

Figure 1. Timing Parameters

Figure 2. External Clock Signal

LP5569 Datasheet(PDF) 8 Page - Texas Instruments

LP5569 Datasheet(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL