5 Description (continued)

The supply voltage (Vpu#) for each channel may be individually set up with a pull up resistor. For example, CH1

may be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).

When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing

bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state

exists between ports. The EN input circuit is designed to be supplied by Vref_A. EN must be LOW to ensure the

high-impedance state during power-up or power-down.

Device Comparison Table

PART

NUMBER

EN

An

Bn

DESCRIPTION

LSF0204D

H

Place all data pins in 3 state mode

(Hi-Z)

Place all data pins in 3 state mode (Hi-Z)

3-state output mode enable

(active Low; referenced to Vref_A)

LSF0204D

L

Input or output

Input or output

LSF0204

H

Input or output

Input or output

3-state output mode enable

(active High, referenced to Vref_A)

LSF0204

L

Place all data pins in 3 state mode

(Hi-Z)

Place all data pins in 3 state mode (Hi-Z)

6 Pin Configuration and Functions

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Vref_A

A1

A2

A3

A4

NC

GND

Vref_B

B1

B2

B3

B4

NC

EN

Figure 6-1. PW Package,

14-Pin TSSOP

(Top View)

A2

A1

A4

A3

NC

Vref_B

Vref_A

B2

B1

B4

B3

NC

EN

GND

1

14

2

3

4

5

6

7

8

9

10

11

12

13

Figure 6-2. RGY Package,

14-Pin VQFN

(Transparent Top View)

Vref_A

A1

A2

A3

A4

GND

Vref_B

B1

B2

B3

B4

EN

1

2

3

4

5

6

7

8

9

10

11

12

Figure 6-3. RUT Package,

12-Pin UQFN

(Transparent Top View)

Figure 6-4. YZP Package,

12-Pin DSBGA

(Transparent Top View)

LSF0204, LSF0204D

SLVSCP5H – JULY 2014 – REVISED APRIL 2021

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