M41T81S datasheet(18/32 Pages) STMICROELECTRONICS

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Clock operation

M41T81S

18/32

Doc ID 10773 Rev 7

When the clock information matches the alarm clock settings based on the match criteria

defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and

SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/SQW pin.

Note:

If the address pointer is allowed to increment to the flags register address, an alarm

condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a

different address. It should also be noted that if the last address written is the “Alarm

Seconds,” the address pointer will increment to the flag address, causing this situation to

occur.

The IRQ/FT/OUT/SQW output is cleared by a READ to the flags register as shown in

Figure 13. A subsequent READ of the flags register is necessary to see that the value of the

alarm flag has been reset to '0.'

The IRQ/FT/OUT/SQW pin can also be activated in the battery backup mode. The

IRQ/FT/OUT/SQW will go low if an alarm occurs and both ABE (alarm in battery backup

mode enable) and AFE are set. Figure 14 illustrates the backup mode alarm timing.

Figure 13.

Alarm interrupt reset waveform

Figure 14.

Backup mode alarm waveform

IRQ/FT/OUT/SQW

ACTIVE FLAG

0Fh

0Eh

10h

HIGH-Z

AI04617

VCC

IRQ/FT/OUT/SQW

ABE and AFE Bits

AF Bit in Flags

HIGH-Z

VSO

VPFD

trec

AI09164b

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