OPA4191IPWT datasheet(35/65 Pages) TI2

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10 Power Supply Recommendations

The OPAx191 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –

40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in Section 6.9.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close

to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply

applications.

– Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

• Make sure to physically separate digital and analog grounds paying attention to the flow of the ground

current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-

effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to

ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. For more detailed

information, refer to Circuit Board Layout Techniques.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 11-2, keeping RF and

RG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• Clean the PCB following board assembly for best performance.

• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced

into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30

minutes is sufficient for most circumstances.

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OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

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OPA4191IPWT Datasheet(PDF) 35 Page - Texas Instruments