SN54AHCT240 datasheet(11/43 Pages) TI2

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6 Detailed Description

6.1 Overview

The SN74AHCT240 devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE)

inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high,

the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by

the current-sinking capability of the driver.

6.2 Functional Block Diagram

1Y1

1OE

1A1

1Y2

1A2

1Y3

1A3

1Y4

1A4

2Y1

2OE

2A1

2Y2

2A2

2Y3

2A3

2Y4

2A4

6.3 Feature Description

• VCC is optimized at 5 V

• Allows up-voltage translation from 3.3 V to 5 V

– Inputs accept VIH levels of 2 V

• Slow edge rates minimize output ringing

• Inputs are TTL-voltage compatible

6.4 Device Functional Modes

Table 6-1. Function Table

(Each 4-bit Inverting Buffer/Driver)

INPUTS

OUTPUT

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SN54AHCT240, SN74AHCT240

SCLS252P – OCTOBER 1995 – REVISED JANUARY 2025

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