SN74LVC74APWR.B datasheet(10/46 Pages) TI2

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7 Detailed Description

7.1 Overview

The SNx4LVC74A devices feature two independent positive-edge triggered D flip-flops. Integrated preset ( PRE)

and clear ( CLR) functions allow for easy setup and control during operation.

The SN54LVC74A device is specified from –55°C to 125°C, and the SN74LVC74A device is specified from

–40°C to 125°C.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of

the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for

down-translation in a mixed-voltage environment.

7.2 Functional Block Diagram

7.3 Feature Description

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of

the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

7.4 Device Functional Modes

Table 7-1 describes the SNx4LVC74A functionality and interactions between the PRE, CLR, CLK, and D inputs.

Table 7-1. Function Table

INPUTS

OUTPUTS

PRE

CLR

CLK

H(1)

↑

SN54LVC74A, SN74LVC74A

SCAS287W – JANUARY 1993 – REVISED DECEMBER 2024

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SN74LVC74APWR.B Datasheet(PDF) 10 Page - Texas Instruments