tc(n)

1/f0

PeriodJitter

PeaktoPeakJitter

1/f0

PRBSINPUT

OUTPUT

CLOCKINPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

tjit(per) = |tc(n) -1/f0|

tjit(pp)

VA -VB

INPUTS

VA -VB

VCM

0.2Vpk

Type2

0.4Vpk

VOH

VCC/2

VOL

VOH

VOL

VCC/2

VOH

VOL

VCC/2

VA

VB

CycletoCycleJitter

VOH

VCC/2

VOL

OUTPUT

tc(n)

tc(n+1)

tjit(cc) =|tc(n) -tc(n+1) |

1V

Type1

A.

All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

B.

The cycle-to-cycle measurement is made on a TEK TDS6604 running TDSJIT3 application software.

C.

All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.

D.

Period jitter and cycle-to-cycle jitter are measured using a 125 MHz 50 ±1% duty cycle clock input. Measured over 75K samples.

E.

Deterministic jitter and random jitter are measured using a 250 Mbps 215–1 PRBS input. Measured over BER = 10-12

Figure 6-12. Receiver Jitter Measurement Waveforms

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SN65MLVD040

SLLS902A – FEBRUARY 2010 – REVISED MARCH 2024

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