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ICS8534AY-01LF Datasheet(PDF) 2 Page - Integrated Device Technology

Part # ICS8534AY-01LF
Description  LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PDF  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8534AY-01LF Datasheet(HTML) 2 Page - Integrated Device Technology

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ICS8534-01
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
2
ICS8534AY-01 REV. A DECEMBER 6, 2007
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number
Name
Type
Description
1, 16, 17, 32,
33, 48, 49, 64
VCCO
Power
Output supply pins for LVPECL outputs.
2, 3, 12, 13
nc
Unused
No connect.
4VCC
Power
Core supply pin for LVPECL outputs.
5
CLK
Input
Pulldown
Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Pulled to 2/3 VCC.
7
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
8
PCLK
Input
Pulldown
Non-inverting differential LVPECL clock input.
9
nPCLK
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. Pulled to 2/3 VCC.
10
VEE
Power
Negative supply pin.
11
OE
Input
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels.
14, 15
nQ21, Q21
Output
Differential clock outputs. LVPECL interface Levels.
18, 19
nQ20, Q20
Output
Differential clock outputs. LVPECL interface Levels.
20, 21
nQ19, Q19
Output
Differential clock outputs. LVPECL interface Levels.
22, 23
nQ18, Q18
Output
Differential clock outputs. LVPECL interface Levels.
24, 25
nQ17, Q17
Output
Differential clock outputs. LVPECL interface Levels.
26, 27
nQ16, Q16
Output
Differential clock outputs. LVPECL interface Levels.
28, 29
nQ15, Q15
Output
Differential clock outputs. LVPECL interface Levels.
30, 31
nQ14, Q14
Output
Differential clock outputs. LVPECL interface Levels.
34, 35
nQ13, Q13
Output
Differential clock outputs. LVPECL interface Levels.
36, 37
nQ12, Q12
Output
Differential clock outputs. LVPECL interface Levels.
38, 39
nQ11, Q11
Output
Differential clock outputs. LVPECL interface Levels.
40, 41
nQ10, Q10
Output
Differential clock outputs. LVPECL interface Levels.
42, 43
nQ9, Q9
Output
Differential clock outputs. LVPECL interface Levels.
44, 45
nQ8, Q8
Output
Differential clock outputs. LVPECL interface Levels.
46, 47
nQ7, Q7
Output
Differential clock outputs. LVPECL interface Levels.
50, 51
nQ6, Q6
Output
Differential clock outputs. LVPECL interface Levels.
52, 53
nQ5, Q5
Output
Differential clock outputs. LVPECL interface Levels.
54, 55
nQ4, Q4
Output
Differential clock outputs. LVPECL interface Levels.
56, 57
nQ3, Q3
Output
Differential clock outputs. LVPECL interface Levels.
58, 59
nQ2, Q2
Output
Differential clock outputs. LVPECL interface Levels.
60, 61
nQ1, Q1
Output
Differential clock outputs. LVPECL interface Levels.
59
nQ0, Q0
Output
Differential clock outputs. LVPECL interface Levels.



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