10 Layout

10.1 Layout Guidelines

• The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended

capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and

a X5R or X7R dielectric.

• The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area

formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 10-1 for a PCB

layout example.

• The connections between the device D1 and D2 pins and the transformer primary endings, and the

connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum

trace inductance.

• • The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-

ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The

capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.

• The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.

• The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.

• The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range

to maximize efficiency.

• The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended

capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and

a X5R or X7R dielectric.

10.2 Layout Example

Figure 10-1. Layout Example of a 2-Layer Board (SN6501)

www.ti.com

SN6501

SLLSEA0I – FEBRUARY 2012 – REVISED JANUARY 2021

Copyright © 2021 Texas Instruments Incorporated

Submit Document Feedback

29

Product Folder Links: SN6501