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SN74LVC1G97DBVT.B Datasheet(PDF) 11 Page - Texas Instruments

Part # SN74LVC1G97DBVT.B
Description  SN74LVC1G97 Configurable Multiple-Function Gate
PDF  40 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

SN74LVC1G97DBVT.B Datasheet(HTML) 11 Page - Texas Instruments

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MCU
(MSP43x)
Temperature
Sensor
EN
VO
VCC = 5 V
Y
VCC
A
LVC1G97
B
GND
Y
MCU
(MSP43x)
A
B
Temperature
Sensor
EN
VO
VCC = 5 V
11
SN74LVC1G97
www.ti.com
SCES416N – DECEMBER 2002 – REVISED JANUARY 2017
Product Folder Links: SN74LVC1G97
Submit Documentation Feedback
Copyright © 2002–2017, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G97 device offers flexible configuration for many design applications. This example describes
basic power sequencing using the AND gate configuration. Power sequencing is often used in applications that
require a processor or other delicate device with specific voltage timing requirements in order to protect the
device from malfunctioning.
Figure 10. Simplified Application
9.2 Typical Application
Figure 11. Typical Application
9.2.1 Design Requirements
•
Recommended input conditions:
–
For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
–
For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
–
Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
•
Recommended output conditions:
–
Load currents must not exceed ±50 mA.
•
Frequency selection criterion:
–
Figure 12 illustrates the effects of frequency on output current.
–
Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout
practices listed in the Layout section.



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