PWM

FLT

Internal

Fault

Signal

FaultDetected

FaultStillPresent

Nofaultpresentduring

entirePWMhigh

interval

. FLTreseton

PWMfallingedge

UCD7232

www.ti.com

SLUSAH3

– MAY 2011

FLT RESET

With the exception of a UVLO fault or a thermal shutdown fault, the FLT flag, once asserted, is cleared by

subsequent PWM pulses. The FLT flag will be cleared on the falling edge of the next PWM pulse, provided a

fault condition is not asserted during the entire on-time of the PWM pulse. If a fault is present or detected during

the on-time interval, the FLT pin will remain asserted. This behavior is illustrated in Figure 6.

Figure 6. FLT Reset Sequence

Whenever the voltage on the VGG pin is below the UVLO falling threshold, as at the time of initial power-up, for

example, the FLT pin will be asserted. When the voltage on the VGG pin rises above the UVLO rising threshold,

the FLT pin will be cleared automatically. This permits the FLT pin to be used as a

“Power Not Good” signal at

initial power-up to signify that there is insufficient gate drive voltage available to permit proper power conversion.

When FLT goes low, it is an indication of

“Gate Drive Power Good” and power conversion can commence. After

initial power-up, the assertion of the FLT flag should be interpreted that power conversion has stopped or has

been limited by a fault condition.

THERMAL SHUTDOWN

If the junction temperature exceeds approximately 165

°C, the device will enter thermal shutdown. This will assert

the FLT pin and both gate drivers will be turned off. When the junction temperature cools by approximately 20

°C,

the device will exit thermal shutdown. The FLT flag is reset upon exiting thermal shutdown.

Gate driver temperature will be strongly influenced by the switching frequency being used, the value of VIN and

VGG, and the total capacitive load on the HS Gate and LS Gate pins. The driver junction temperature is not

normally strongly affected by load current. However, a rise in the PCB substrate temperature due to load current

induced power dissipation in nearby components will raise the junction temperature and contribute to a possible

thermal shutdown event.

Copyright

© 2011, Texas Instruments Incorporated

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