P

1

P

2

EA

OUT

R

R

K

R

R

1 K

V

where K

VOUT_SCALE_LOOP

V

=

=

-

=

@

SW

P

1

C2

2

0.35

F

R

=

p ´

´

´

2

1

2

EA

OUT

OFFSET

1

2

1

2

1

2

1

2

EA

EA

R

R R

V

V

I

R R

R R

R

R

R

R

R

R

=

+

æ

ö

æ

ö

+

+

+

+

ç

÷

ç

÷

è

ø

è

ø

UCD9244

www.ti.com

SLVSAL6A

– NOVEMBER 2010 – REVISED FEBRUARY 2011

Voltage Sense Filtering

Conditioning should be provided on the EAP and EAN signals. Figure 12 shows a divider network between the

output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output

voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the

signal conditioned by the low-pass filter formed by R1 and C2.

As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly

across an output capacitor as close to the load as possible. Route the positive and negative differential sense

signals as a balanced pair of traces or as a twisted pair cable back to the controller. Put the divider network close

to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the

voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss

and minimizing interference susceptibility. A parallel resistance (Rp) of 1kΩ to 4kΩ is a good compromise. Once

RP is chosen, R1 and R2 can be determined from the following formulas.

(2)

It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an

additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter,

the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:

(3)

To obtain the best possible accuracy, the input resistance and offset current on the device should be considered

when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the

UCD9244. The input resistance and input offset current are specified in the parametric tables in this datasheet.

VEA = VEAP – VEAN in the equation below.

(4)

The effect of the offset current can be reduced by making the resistance of the divider network low.

Digital Compensator

Each voltage rail controller in the UCD9244 includes a digital compensator. The compensator consists of a

nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter

section cascaded with a first order IIR filter section.

The Texas Instruments Fusion Digital Power

™ Designer development tool can be used to assist in defining the

compensator coefficients. The design tool allows the compensator to be described in terms of the pole

frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power

™

Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based

on the total loop gain for each feedback system. The coefficients of the filter sections are generated through

modeling the power stage and load.

Additionally, the UCD9244 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or

tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is

below the configured light load threshold.

© 2010–2011, Texas Instruments Incorporated

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