STM32WBA62CGF7 datasheet(35/185 Pages) STMICROELECTRONICS

35 / 185 page

DS14736 Rev 1

35/185

STM32WBA6xxx

Functional overview

By default, the microcontroller is in Run mode after a system or a power on reset. It is up to

the user to select one of the low-power modes described below:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt or event occurs.

•

Stop 0 and Stop 1 modes

Stop modes achieve the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the HSI16,

and the HSE32 crystal oscillators are disabled. The LSE or LSI is still running.

The RTC, TAMP, IWDG and SLEEP_TIMER can remain active.

Some peripherals are autonomous and can operate in Stop modes by requesting their

kernel clock and their bus clock when needed, to transfer data with DMA Stop 0 modes

will be entered. Refer to PWR background autonomous mode (BAM) for more details.

In Stop modes the bus clocks when requested use HSI16.

Stop 0 offer the largest number of active peripherals, with or without DMA, and wake-up

sources, a smaller wake-up time but a higher consumption than Stop 1.

In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time, but

with higher power consumption.

Stop 1 is the lowest power mode with full retention, but the functional peripherals and

sources of wake-up are reduced.

The BOR can be configured in ultra-low-power mode to further reduce consumption

during Stop 1 mode.

The system clock when exiting from Stop 0 or Stop 1 modes is HSI16.

•

Stop 2 mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and some registers. All clocks in the VCORE domain are stopped, the PLL, the

HSI16, and the HSE32 crystal oscillators are disabled. The LSE or LSI is still running.

The RTC, TAMP, IWDG and SLEEP_TIMER can remain active.

A reduced set of peripherals are autonomous and can operate in Stop 2 mode by

requesting their kernel clock and their bus clock when needed. Refer to PWR

background autonomous mode (BAM) for more details.

Stop 2 is the lowest power mode with partial retention, but the functional peripherals

and sources of wake-up are reduced.

The BOR can be configured in ultra-low-power mode to further reduce power

consumption during Stop 2 mode.

The system clock when exiting from Stop 2 modes is HSI16.

STM32WBA62CGF7 Datasheet(PDF) 35 Page - STMicroelectronics

STM32WBA62CGF7 Datasheet(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL