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TAS5713 Datasheet(PDF) 26 Page - Texas Instruments |
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TAS5713 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 72 page ![]() SCLK 16Clks LRCLK LeftChannel 16-BitMode 1 1 15 15 14 14 MSB LSB 16Clks RightChannel 2-ChannelI S(PhilipsFormat)StereoInput 2 T0266-01 3 3 2 2 5 5 4 4 9 9 8 8 0 13 13 10 10 11 11 12 12 SCLK MSB LSB 23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 19 18 20-BitMode 16-BitMode 15 14 MSB LSB 32Clks RightChannel 2-ChannelLeft-JustifiedStereoInput T0034-02 4 5 9 8 1 4 5 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 4 5 9 8 1 4 5 1 0 0 0 SCLK TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com NOTE: All data presented in 2s-complement form with MSB first. Figure 34. I2S 32-fS Format Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. NOTE: All data presented in 2s-complement form with MSB first. Figure 35. Left-Justified 64-fS Format 26 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TAS5713 |
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