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TNETV2507ANPGE Datasheet(PDF) 32 Page - Texas Instruments |
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TNETV2507ANPGE Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 142 page  Functional Overview 32 April 2004 − Revised January 2008 SPRS244J 3.1.3 On-Chip Read-Only Memory (ROM) The one-wait-state ROM is located at the byte address range FF0000h−FFFFFFh, for a total of 64K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM. The standard 5507 device includes a bootloader program resident in the ROM. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory map, and byte address range FF0000h−FFFFFFh is directed to external memory space. A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect the MPNMC bit. The on-chip ROM can be accessed by the program, data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two cycles per 16-bit word. |
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