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CY8CKIT-059 Datasheet(PDF) 25 Page - Infineon Technologies AG |
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CY8CKIT-059 Datasheet(HTML) 25 Page - Infineon Technologies AG |
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25 / 140 page  Document Number: 001-84932 Rev. *N Page 24 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-1. Clocking Subsystem 4-25 MHz ECO 3-74 MHz IMO 32 kHz ECO 1,33,100 kHz ILO s k e w 7 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit Bus Clock Divider 16 bit 48 MHz Doubler for USB 24-80 MHz PLL System Clock Mux External IO or DSI 0-33 MHz s k e w Analog Clock Divider 16 bit s k e w Analog Clock Divider 16 bit s k e w Analog Clock Divider 16 bit Bus Clock CPU Clock |
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