TMS320F28026PTS datasheet(60/147 Pages) TI2

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The PLL-based clock module provides four modes of operation:

• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock

for the Watchdog block, core and CPU-Timer 2

• INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock

for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen

for the Watchdog block, core and CPU-Timer 2.

• Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/

resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2

pins. Some devices may not have the X1/X2 pins. See Section 7.2.1 for details.

• External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be

bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. The

XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or

GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input

(forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable

at boot time.

Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock

source must be disabled (using the CLKCTL register) before switching clocks.

Table 9-16. Possible PLL Configuration Modes

PLL MODE

REMARKS

PLLSTS[DIVSEL]

CLKIN AND

SYSCLKOUT

PLL Off

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

is disabled in this mode. This can be useful to reduce system noise and for low-

power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN.

0, 1

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Bypass

PLL Bypass is the default PLL configuration upon power-up or after an external

reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or

while the PLL locks to a new frequency after the PLLCR register has been

modified. In this mode, the PLL is bypassed but the PLL is not turned off.

0, 1

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Enable

Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the

PLLCR the device will switch to PLL Bypass mode until the PLL locks.

0, 1

OSCCLK * n/4

OSCCLK * n/2

OSCCLK * n/1

9.6.4 Loss of Input Clock (NMI Watchdog Function)

The 2802x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the

on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and

PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This

limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.

When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.

Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or

the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status

(MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and

initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a

shut-down procedure for the system.

If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a

preprogrammed time interval. Figure 9-11 shows the interrupt mechanisms involved.

TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026

TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023

TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200

SPRS523P – NOVEMBER 2008 – REVISED FEBRUARY 2021

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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-

Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200

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