TPS2069CDBVT datasheet(22/50 Pages) TI2

22 / 50 page

Via to Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal

TPS2000C, TPS2001C, TPS2041C, TPS2051C, TPS2061C

TPS2065C, TPS2065C-2, TPS2068C, TPS2069C, TPS2069C-2

SLVSAU6H – JUNE 2011 – REVISED APRIL 2016

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Product Folder Links: TPS2000C TPS2001C TPS2041C TPS2051C TPS2061C TPS2065C TPS2065C-2 TPS2068C

TPS2069C TPS2069C-2

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11 Layout

11.1 Layout Guidelines

1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low

inductance trace.

2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections

using a low inductance trace.

3. The PowerPAD must be directly connected to PCB ground plane using wide and short copper trace.

11.2 Layout Example

Figure 42. Recommended Layout

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the

TPS20xxC and TPS20xxC-2. The system designer can control choices of package, proximity to other power

dissipating devices, and printed-circuit board (PCB) design based on these calculations. These have a direct

influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature,

are often determined by system considerations. It is important to remember that these calculations do not include

the effects of adjacent heat sources, and enhanced or restricted air flow.

Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and

maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the

pad improve the efficiency and reliability of both TPS20xxC and TPS20xxC-2 parts and the system. The following

examples were used to determine the

θJACustom thermal impedances noted in Thermal Information: SOT-23

and Thermal Information: MSOP-PowerPAD. They were based on use of the JEDEC high-k circuit board

construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.

While TI recommends that the DGN package PAD be soldered to circuit board copper fill and vias for low thermal

impedance, there may be cases where this is not desired. For example, use of routing area under the IC. Some

devices are available in packages without the PowerPad (DGK) specifically for this purpose. The

θJA for the DGN

package with the pad not soldered and no extra copper, is approximately 141°C/W for 0.5-A and 1-A rated parts,

and 139°C/W for the 1.5-A and 2-A rated parts. The

θJA for the DGK mounted per Figure 45 is 110.3°C/W. These

values may be used in Equation 1 to determine the maximum junction temperature.

TPS2069CDBVT Datasheet(PDF) 22 Page - Texas Instruments