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AM625 Datasheet(PDF) 1 Page - Texas Instruments |
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AM625 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 276 page  AM62x Sitara™ Processors 1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Arm® Cortex®-M4F MCU at up to 400MHz – 256KB SRAM with SECDED ECC • Dedicated Device/Power Manager Multimedia: • Display subsystem – Dual display support – 1920x1080 @ 60fps for each display – 1x 2048x1080 + 1x 1280x720 – Up to 165MHz pixel clock support with Independent PLL for each display – OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS) – Support safety feature such as freeze frame detection and MISR data check • 3D Graphics Processing Unit – 1 pixel per clock or higher – Fillrate greater than 500Mpixels/sec – >500MTexels/s, >8GFLOPs – Supports at least 2 composition layers – Supports up to 2048x1080 @60fps – Supports ARGB32, RGB565 and YUV formats – 2D graphics capable – OpenGL ES 3.1, Vulkan 1.2 • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY – MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2 – Support for 1,2,3 or 4 data lane mode up to 1.5Gbps per lane – ECC verification/correction with CRC check + ECC on RAM – Virtual Channel support (up to 16) – Ability to write stream data directly to DDR via DMA Memory Subsystem: • Up to 816KB of On-chip RAM – 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks – 256KB of On-chip RAM with SECDED ECC in SMS Subsystem – 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware – 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem – 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem • DDR Subsystem (DDRSS) – Supports LPDDR4, DDR4 memory types – 16-Bit data bus with inline ECC – Supports speeds up to 1600MT/s – Max addressable range • 8GBytes with DDR4 • 4GBytes with LPDDR4 Functional Safety: • Functional Safety-Compliant targeted [Automotive] – Developed for functional safety applications – Documentation will be available to aid ISO 26262 functional safety system design – Systematic capability up to ASIL D targeted – Hardware integrity up to ASIL B targeted – Safety-related certification • ISO 26262 by TUV SUD planned • AEC - Q100 qualified AM625, AM625-Q1, AM623, AM620-Q1 SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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