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TUSB9261

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SLLSE67I – MARCH 2011 – REVISED MARCH 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

(1)

Sigma value assuming Gaussian distribution

(2)

After application of JTF

(3)

Calculated as 14.1 × RJ + DJ

(4)

Absolute phase jitter (p-p)

6.8 Oscillator Specification

XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground

plane. A 40-MHz clock can be used.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CXI

XI input capacitance

TJ = 25°C

0.414

pF

VIL

Low-level input voltage

0.7

V

VIH

High-level input voltage

1.05

V

Ttosc_i

Frequency tolerance

Operational temperature

–50

50

ppm

Tduty

Duty cycle

45%

50%

55%

TR/TF

Rise/fall time

20% to 80%

6

ns

RJ

Reference clock

JTF (1 sigma)(1)(2)

0.8

ps

TJ

Reference clock

JTF (total p-p)(2)(3)

25

ps

Tp-p

Reference clock jitter

(Absolute p-p)(4)

50

ps

6.9 Crystal Specification

A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB

ground plane. A 40-MHz crystal can be used.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Oscillation mode

Fundamental

ƒO

Oscillation frequency

40

MHz

ESR

Equivalent series resistance

40 MHz

50

Ω

Ttosc_i

Frequency tolerance

Operational temperature

±50

ppm

Frequency stability

1 year aging

±50

ppm

CL

Load capacitance

12

20

24

pF

CSHUNT

Crystal and board stray capacitance

4.5

pF

Drive level (max)

0.8

mW