LP5024 datasheet(41/59 Pages) TI2

41 / 59 page

The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are

normally located on the bus master). In typical applications, values of 1.8kΩ to 4.7kΩ are used.

VCAP is internal LDO output pin. This pin must be connected through a 1µF capacitor to GND. Place the

capacitor as close to the device as possible.

TI recommends having a 1µF capacitor between VCC and GND to ensure proper operation. Place the capacitor

as close to the device as possible.

8.2.3 Application Curves

The test condition for Figure 9-2 is that the testing is under bank control, using the following register values: 0x02

(0xFF), 0x04 (0xA0), 0x05 (0xA0), 0x06 (0xA0).

The test condition for Figure 9-2 is that the testing is under bank control, using the following register values: 0x02

(0xFF), 0x04 (0x10), 0x05 (0x10), 0x06 (0x10).

Figure 8-2. Current Waveform of OUT0, OUT1,

OUT2 and OUT3

Figure 8-3. Current Waveform of OUT0, OUT1,

OUT2 and OUT3

8.3 Power Supply Recommendations

The device is designed to operate from a VVCC input-voltage supply range between 2.7V and 5.5V. This input

supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input

supply rail must be low enough that the input-current transient does not cause a drop below a 2.7V level in the

LP50xx VVCC supply voltage.

8.4 Layout

8.4.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across

the output channels is high, the device power dissipation can be large. The LP50xx device has very good

thermal performance because of the thermal pad design; however, the PCB layout is also very important to

ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is

essential for the long-term reliability of the device.

Use the following guidelines when designing the device layout:

• Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends to put the ground

plane as Figure 8-4, Figure 8-5 and Figure 8-6.

• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major

heat flow path from the package to the ambient is through copper on the PCB. Maximum copper density is

extremely important when no heat sinks are attached to the PCB on the other side from the package.

www.ti.com

LP5018, LP5024

SLVSEB8C – OCTOBER 2018 – REVISED JULY 2024

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LP5024 Datasheet(PDF) 41 Page - Texas Instruments